The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to a credit mechanism utilized to access multiple banks of shared cache.
To improve performance, some processors utilize multiple cores on a single die. A die may also include a cache that can be shared by multiple cores. As additional cores are provided on the same die, a shared on-die cache may become a performance bottleneck. Some designs utilize circuitry within each core to manage the cores' shared cache access. Hence, each time a cache design changes, cores need to also be redesigned or re-floor planned. This may lengthen a processor's design cycle, or increase its design complexity.